The present invention relates to a semiconductor device and a semiconductor package, and more particularly, to a semiconductor device and a semiconductor package having the same, including a decoupling capacitor.
A power ground grid noise may occur in a semiconductor device, when current is consumed abruptly and a plurality of signals are inputted/outputted simultaneously. As an integration degree and an operation speed of the semiconductor device increase, an amount of the power ground grid noise increases. Typically, a decoupling capacitor has been used to remove the power ground grid noise. The decoupling capacitor connects between a region for providing a power voltage (VDD) and a region for providing a ground voltage (VSS) and acts as a power storage tank. The use of the decoupling capacitor can remove the power ground grid noise, thereby stably supplying a power to the semiconductor device.
FIG. 1 is a view illustrating a layout of internal circuits 101 and a decoupling capacitor in a conventional semiconductor device.
As shown in FIG. 1, the internal circuits 101 process signals inputted into the semiconductor device 100. For example, the internal circuits 101 may be a circuit for storing data. The decoupling capacitor is deployed on a region A 103, on which the internal circuits 101 is not arranged.
Since a capacitance of the decoupling capacitor configured generally as a Metal Oxide Semiconductor (MOS) is very small, a plurality of the decoupling capacitors are arranged on the A region 103 to minimize the amount of the power ground grid noise and thus enough capacitance is ensured.
Meanwhile, as aforementioned, as the operation speed of the semiconductor device 100 increases and an amount of the power ground grid noise increases, there is a need to deploy more decoupling capacitors on the region A 103 in order to minimize the power ground grid noise. Accordingly, an increased space for deploying the more decoupling capacitors is necessary on the region A 103 and the increased space causes to limit an area of the semiconductor device.
Additionally, since the decoupling capacitor has to be arranged on the region A 103, on which the internal circuits 101 are not arranged, the space for deploying the decoupling capacitor is limited.